PUBLICATIONS « Home Page of Dr. Himanshu Thapliyal

PUBLICATIONS

August 16th, 2014 by hthapliyal

SELECT PUBLICATIONS/PATENT:

BOOK CHAPTER:

  1. H. Thapliyal, N. Ranganathan and S.Kotiyal, “Reversible Logic Based Design and Test of Field Coupled Nanocomputing Circuits”,  Springer Lecture Notes on Computer Science State-ofthe-Art-Survey Series Special Volume on Field-Coupled Nanocomputing, 2014

 JOURNAL PUBLICATIONS:

  1. S. Kotiyal H. Thapliyal and N. Ranganathan, “Efficient Reversible NOR Gates and Their All Optical MZI Based Design“, Microelectronics Journal, Vol. 6, pp. 825-834, Aug 2013.
  2. H. Thapliyal and N. Ranganathan, “Design of Efficient Reversible Logic Based Binary and BCD Adder Circuits”, ACM Journal of Emerging Technologies in Computing Systems,Vol.9, No.3,pp. 17:1–17:31, Sep 2013.
  3. H. Thapliyal, N. Ranganathan and S.Kotiyal, “Design of Testable Reversible Sequential Circuits “, IEEE Transactions on VLSI, vol. 21, no.7, pp.1201-1209, July 2013
  4. H.Thapliyal, H. V. Jayashree, A. N. Nagamani, H.R. Arabnia, “Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead Adder”, Springer Transactions on Computational Science XVII Lecture Notes in Computer Science Volume 7420, 2013, pp 73-97
  5. H. Thapliyal and N. Ranganathan, “Design of Reversible Sequential Circuits Optimizing Quantum Cost, Delay and Garbage Outputs”, ACM Journal of Emerging Technologies in Computing Systems, Vol. 6, No. 4, Article 14, Dec 2010
  6. H. Thapliyal and N. Ranganathan, “Reversible Logic Based Concurrently Testable Latches for Molecular QCA”, IEEE Transactions on Nanotechnology, vol. 9, No. 1, pp. 62-69, Jan 2010.
  7. H. Thapliyal, H.R. Arabnia and M.B. Srinivas, “Efficient Reversible Logic Design of BCD Subtractors”, Springer Transactions on Computational Sciences Journal, Vol. 3, LNCS 5300, pp. 99-121, 2009.

 

CONFERENCES:

  1. H.V. Jayashree, H. Thapliyal and V. Agrawal, “Design of Dedicated Reversible Quantum Circuitry for Square Computation”, Proceedings of the 27th International Conference on VLSI Design (VLSI Design), Mumbai, India, Jan 2014, pp. 551-556.
  2. S. Kotiyal H. Thapliyal and N. Ranganathan, “Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits”, Proceedings of the 27th International Conference on VLSI Design (VLSI Design), Mumbai, India, Jan 2014, pp. 545-550.
  3. H.Thapliyal, A. Bhatt and N. Ranganathan, “A New CRL Gate As a Super Class of Fredkin Gate for Design of Reversible Barrel Shifter”,   Proceedings of the 56th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Columbus, Aug 2013, pp. 1067-1070.
  4. H.Thapliyal and N. Ranganathan, “Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies “,   Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Amherst, Aug 2012, pp. 5-6. (Best Paper Award at Ph.D. Forum)
  5. S.Kotiyal, H.Thapliyal and N. Ranganathan, “Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates “,   Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Amherst, Aug 2012, pp. 207-212.
  6. S.Kotiyal, H.Thapliyal and N. Ranganathan, “Mach-Zehnder Interferometer Based Design of All Optical Reversible Binary Adder”,       Proceedings of the Design Automation and Test in Europe (DATE), Dresden, Germany, March 2012, pp. 721-726.
  1. H. Thapliyal and N. Ranganathan, “A new design of the reversible subtractor circuit”, Proceedings of the 11th IEEE International Conference on Nanotechnology (IEEE NANO), Portland, Oregon, August 2011, pp.1430-1435.
  2. S. Kotiyal, H. Thapliyal, and N. Ranganathan, “Design of a reversible bidirectional barrel shifter”, Proceedings of the   11th IEEE International Conference on Nanotechnology (IEEE NANO), Portland, Oregon, August 2011, 463-468.
  3. M. Nachtigal, H. Thapliyal, and N. Ranganathan, “Design of a reversible floating-point adder architecture”, Proceedings of the 11th IEEE International Conference on Nanotechnology (IEEE NANO), Portland, Oregon, August 2011, pp. 451-456.
  4. H. Thapliyal and N. Ranganathan, “ A New Reversible Design of BCD Adder”, Proceedings of Design Automation and Test in Europe (DATE), Grenoble, France, March 2011, pp.1180-1183.
  5. H. Thapliyal, N. Ranganathan and R. Ferreira, “Design of a Comparator Tree Based on Reversible Logic”, Proceedings of the 10th IEEE International Conference on Nanotechnology (IEEE NANO), Seoul, Korea, Aug 2010, pp. 1113-1116.
  6. H. Thapliyal and N.Ranganathan, “Reversible Logic Based Concurrent Error Detection Methodology For Emerging Nanocircuits”, Proceedings of the 10th IEEE International Conference on Nanotechnology (IEEE NANO),Seoul, Korea, Aug 2010, pp.217-222.
  7. M. Nachtigal, H. Thapliyal and N. Ranganathan, “Design of a Reversible Single Precision Floating Point Multiplier Based on Operand Decomposition”,   Proceedings of the 10th IEEE International Conference on Nanotechnology (IEEE NANO), Seoul, Korea, Aug 2010,pp.233-237.
  8. S. Kotiyal, H. Thapliyal and N. Ranganathan, “Design of A Ternary Barrel Shifter Using Multiple-Valued Reversible Logic”, Proceedings of the 10th IEEE International Conference on Nanotechnology (IEEE NANO), Seoul, Korea, Aug 2010,pp.1104-1108.
  9. H. Thapliyal and N. Ranganathan, “Design of Reversible Latches Optimized for Quantum Cost,Delay and Garbage Outputs”, Proceedings of the 23rd International Conference on VLSI Design (VLSI Design) , Bangalore, India, Jan 2010,pp.235-240
  10. H. Thapliyal and N. Ranganathan, ”Bit Conserving Logic as a Potential Integration Platform for Hybrid Molecular & Nanoscale CMOS-Based Architectures”, Proceedings of the 2009 Nanoelectronic Devices for Defense & Security (NANO-DDS) Conference, Fort Lauderdale, Sept 2009.
  11. H. Thapliyal and N. Ranganathan, “Concurrently Testable FPGA Design for Molecular QCA Using Conservative Reversible Logic Gate”, Proceedings of the International Symposium on Circuits and Systems (ISCAS), Taipei, May 2009, pp. 1815 – 1818.
  12. H. Thapliyal and N. Ranganathan, “Design of Efficient Reversible Binary Subtractors Based on A New Reversible Gate “,   Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, May 2009, pp.239-234.
  13. H. Thapliyal and N. Ranganathan, ” Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits”,  Proceedings of the 22nd International Conference on  VLSI Design (VLSI Design), Delhi, India, Jan 2009, pp.511-516. (Acceptance Rate: 18.43%, 59 regular papers from 320 submissions).
  14. H. Thapliyal and N. Ranganathan, “Testable Reversible Latches for Molecular QCA”, Proceedings of the 8th International Conference on Nanotechnology (IEEE NANO), Arlington, TX, Aug 2008. pp. 699-702 (Invited Paper).
  15. H. Thapliyal and A. P. Vinod, “Design of Reversible Sequential Elements with Feasibility of Transistor Implementation”, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), New Orleans, USA, May 2007, pp. 625-628
  16. H. Thapliyal and A. P. Vinod, “Designing Efficient Online Testable Reversible Adders with New Reversible Gate”, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), New Orleans, USA, May 2007, pp.1085-1088
  17. H. Thapliyal, H. R. Arabnia, R. Bajpai, K. K. Sharma, “Combined Integer and Variable Precision (CIVP) Floating Point Multiplication Architecture for FPGAs”, Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA 2007), Las Vegas, Nevada, USA, June 2007, pp.449-450
  18. H. Thapliyal, H.R. Arabnia and A.P.Vinod, “Combined Integer and Floating Point Multiplication Architecture (CIFM) for FPGAs and its Reversible Logic Implementation”, Proceedings of the 49th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Puerto Rico,  Aug 2006,
    pp. 438-442 (Best Student Paper Award Finalist).
  19. H. Thapliyal and M.B Srinivas, “Reversible Logic Implementation of BCD Subtractor for IEEE 754r Format”, Proceedings of the 15th ACM SIGDA International Workshop on Logic & Synthesis (IWLS ), Colorado, USA, June 7-9, 2006.
  20. H. Thapliyal and M. Zwolinski, “Reversible Logic to Cryptographic Hardware: A New Paradigm”, Proceedings of the 49th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Puerto Rico, Aug 2006, pp. 342-346 (Best Student Paper Award Finalist).
  21. H. Thapliyal and M.B. Srinivas, “The New BCD Subtractor and Its Reversible Logic Implementation”, Springer-Verlag Lecture Notes in Computer Science, Proceedings of the 11th Asia-Pacific Computer Systems Architecture Conference – ACSAC, Vol. 4186/2006, pp. 469-475, Sep 2006
  22. H. Thapliyal and M.B. Srinivas et al., “Modified Montgomery Modular Multiplication Using 4:2 Compressor And CSA Adder”, Proceedings of the 3rd IEEE International Workshop on Electronic Design, Test and Applications (DELTA) , Kuala Lumpur, Malaysia, Jan 2006, pp. 414-417.
  23. H. Thapliyal, S. Kotiyal and M.B. Srinivas, “Novel BCD Adders and their Reversible Logic Implementation for IEEE 754r Format”, Proceedings of the 19th  IEEE/ACM International Conference on VLSI Design (VLSI Design), Hyderabad, India, Jan 4-7, 2006, pp. 387-392.
  24. H. Thapliyal and M.B. Srinivas, “Novel Reversible “TSG” Gate and Its Application for Designing Reversible Carry Look Ahead Adder and Other Adder Architectures”, Springer-Verlag Lecture Notes in Computer Science , Proceedings of the 10th Asia-Pacific Computer Systems Architecture Conference – ACSAC,vol. 3740/2005, pp. 775-786, October 2005
  25. H.  Thapliyal, M. B. Srinivas and M. Zwolinski, “A Beginning in the Reversible Logic Synthesis of Sequential Circuits,” Proceedings of NASA Military and Aerospace Programmable Logic Devices (MAPLD) International Conference, Sep 2005.