Hardware Security « Home Page of Dr. Himanshu Thapliyal

Hardware Security

Link: Google Scholar Profile

  • H. Thapliyal, T.S.S. Varun, S.D. Kumar, “UTB-SOI Based Adiabatic Computing for Low-Power and Secure IoT Devices”, Proceedings of the 12th Annual Cyber and Information Security Research Conference, 2017.  (Best Paper Award)
  • H. Thapliyal, T.S.S. Varun, S.D. Kumar, “Adiabatic Computing for Low Power and DPA Resistant Lightweight Cryptography for IoT Applications”, Accepted in 2017 Design Automation Conference (DAC), Work-in-Progress Session, Austin, June 2017
  • S.D. Kumar, H. Thapliyal, and A. Mohammad, “FinSAL: FinFET Based Secure Adiabatic Logic for Energy-Efficient and DPA Resistant IoT Devices”, IEEE Transactions on Transactions on Computer-Aided Design of Integrated Circuits and Systems, Feb 2017.  DOI: 10.1109/TCAD.2017.2685588
  • S.D. Kumar, H. Thapliyal, and A. Mohammad, “EE-SPFAL: A Novel Energy-Efficient Secure Positive Feedback Adiabatic Logic for DPA Resistant RFID and Smart Card”, IEEE Transactions on Emerging Topics in Computing: Special Issue on Emerging Technologies in Computer Design, vol. PP, no. 99, pp. 1–1, 2016 (Invited top ranked submissions of the 34th International Conference on Computer Design (ICCD), Oct 2016). DOI: 10.1109/TETC.2016.2645128 
  • S.D. Kumar, H. Thapliyal, A. Mohammad, and K.S. Perumalla, “Design Exploration of Symmetric Pass Gate Adiabatic Logic for Energy-Efficient and Secure Hardware”, Integration, VLSI Journal, Available online Sep 17, 2016: DOI: http://dx.doi.org/10.1016/j.vlsi.2016.08.007
  • S. D. Kumar and H. Thapliyal, “QUALPUF: A Novel Quasi-Adiabatic Logic based Physical Unclonable Function,” Proceedings of the 11th Annual Cyber and Information Security Research Conference, 2016, p. 24.  DOI:>10.1145/2897795.2897798 
  • S.D. Kumar, H. Thapliyal, A. Mohammad, “Symmetric Pass Gate Adiabatic Logic for Low Power and DPA Resistant RFID and Smart Card”, poster presentation in 18th Conference on Cryptographic Hardware and Embedded Systems (CHES 2016), Santa Barbara, Aug 2016
  • H. Thapliyal and M. Zwolinski, “Reversible Logic to Cryptographic Hardware: A New Paradigm”, Proceedings of the 49th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Puerto Rico, Aug 2006, pp. 342-346 DOI: 10.1109/MWSCAS.2006.382067 
  • H. Thapliyal and M.B. Srinivas et al., “Modified Montgomery Modular Multiplication Using 4:2 Compressor And CSA Adder”, Proceedings of the  3rd IEEE International Workshop on Electronic Design, Test and Applications (DELTA) , Kuala Lumpur, Malaysia, Jan 2006, pp. 414-417.  DOI : http://doi.ieeecomputersociety.org/10.1109/DELTA.2006.70