Honors/Service « Home Page of Dr. Himanshu Thapliyal

Honors/Service

  • Invited five days course at IIT Roorkee, India as  international expert on “Logic Design under Paradigm of Rebooting Computing” under Global Initiative for Academic Networks (GIAN) sponsored by Government of India. 
  • Best Paper Award 2017:  UTB-SOI Based Adiabatic Computing for Low-Power and Secure IoT Devices, 12th Annual Cyber and Information Security Research Conference, 2017
  • Editorial Board Member: Microelectronics Journal
  • Executive Editor: IEEE Consumer Electronic Magazine
  • Most Popular Article: “Design of Testable Reversible Sequential Circuits” among top 25 most popular articles in IEEE Transactions on VLSI, 2014 and 2015.
  • Steering Committee: The International Symposium on Nanoelectronics and Information Systems, Dec 2015
  • Qualstar Award from Qualcomm, April 2014 for outstanding contributions in Memory BIST.
  • Best Paper Award 2012:  Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies, IEEE Computer Society Annual Symposium on VLSI, 2012
  • News on Ph.D. Dissertation work featured in MIT Technology Review, ACM TechNews, etc.
  • 2010 UPE/CS Award for Academic Excellence from the Upsilon Pi Epsilon Honor Society for the Computing Sciences and the IEEE computer Society
  • 2010 Richard E. Merwin Scholarship, as a recognition of exemplary involvement in student chapter activities, excellent academic achievement and willingness to act as a student ambassador
  • 2009 Distinguished Graduate Achievement Award, from the Graduate and Professional Student Council, University  of South Florida, Tampa
  • Invited Paper in IEEE NANO Conference, Dallas, Texas, Aug 2008.
  • Best Student Paper Award Finalist in top 12 from 320 accepted submissions, IEEE MWSCAS, Aug 2006. Paper title: ‘Combined Integer and Floating Point Multiplication Architecture (CIFM) for FPGAs and its Reversible Logic Implementation’
  • Best Student Paper Award Finalist in top 12 from 320 accepted submissions, IEEE MWSCAS, Aug 2006. Paper title: ‘Reversible Logic to Cryptographic Hardware: A New Paradigm’