Nanocomputing « Home Page of Dr. Himanshu Thapliyal

Nanocomputing

Link: Google Scholar Profile

                       Circuits for Quantum Computing, Magnetic Computing,                         and Emerging Technologies

US PATENT

  • Conservative Logic Element for Design of Quantum Dot Cellular Automata Circuits, N. Ranganathan and H. Thapliyal, United States Patent 7880496, Feb 2011

TUTORIALS

  • H.Thapliyal and N. Ranganathan, “Reversible Logic: Basics,  Prospects in Emerging Nanotechnologies and Challenges in Future”,  Tutorial at 55th International Midwest Symposium on Circuits and systems (IEEE MWSCAS 2012), Boise, Idaho, August 5-8, 2012
  • H.Thapliyal and N. Ranganathan, “Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future”,  Tutorial at 25th International Conference on VLSI Design (VLSI Design), Hyderabad, India, Jan 2012, pp. 13-15

 

YEAR 2017

  • H. V. Jayashree, H. Thapliyal, and V. K. Agrawal, “Efficient Circuit Design of Reversible Square,” Transactions on Computational Science XXIX, pp 33-46, March 2017.
  • V. Mishra and H. Thapliyal, “Heuristic based Majority/minority Logic Synthesis for Emerging Technologies”, Proceedings of the 30th IEEE International Conference on VLSI Design (VLSI Design), Hyderabad, India, Jan 2017.

YEAR 2016

  • F. Sharifi, A. Panahi, H. Sharifi, K. Navi, N. Bagherzadeh, and H. Thapliyal, “Design of quaternary 4–2 and 5–2 compressors for nanotechnology,” Computers & Electrical Engineering, vol. 56, pp. 64–74, Nov. 2016.
  • M. H. A. Khan, H. Thapliyal, and E. Munoz-Coreas, “Automatic synthesis of quaternary quantum circuits,” The Journal of Supercomputing, Sep. 2016.
  • H. Thapliyal, “Mapping of Subtractor and Adder-Subtractor Circuits on Reversible Quantum Gates,” in Transactions on Computational Science XXVII, M. L. Gavrilova and C. J. K. Tan, Eds. Springer Berlin Heidelberg, 2016, pp. 10–34.
  • S. Kotiyal and H. Thapliyal, “Design Methodologies for Reversible Logic Based Barrel Shifters,” Journal of Circuits, Systems and Computers, vol. 25, no. 02, p. 1650003, Feb. 2016.
  • H. Thapliyal, C. Labrado, and K. Chen, “Design procedures and NML cost analysis of reversible barrel shifters optimizing garbage and ancilla lines,” The Journal of Supercomputing, vol. 72, no. 3, pp. 1092–1124, Mar. 2016.
  • H. V. Jayashree, H. Thapliyal, H. R. Arabnia, and V. K. Agrawal, “Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier,” The Journal of Supercomputing, vol. 72, no. 4, pp. 1477–1493, Apr. 2016.
  • H. Thapliyal and C. Labrado, “Design of adder and subtractor circuits in majority logic-based field-coupled QCA nanocomputing,” Electronics Letters, vol. 52, no. 6, pp. 464–466, Mar. 2016.
  • C. Labrado and H. Thapliyal, “Design of a multilayer five-input majority gate and adder/subtractor circuits in NML computing,” Electronics Letters, vol. 52, no. 19, pp. 1618–1620, 2016.

YEAR 2015-2014

  •  A. Roohi, H Thapliyal and R Demara, “Wire Crossing Constrained QCA Circuit Design using Bilayer Logic Decomposition”, IET Electronics Letters,  vol. 51, no. 21, pp. 1667–1669, Oct. 2015.
  •  S. Kotiyal, H. Thapliyal and N. Ranganathan, “Reversible logic based multiplication computing unit using binary tree data structure”, The Journal of Supercomputing,  vol. 71, no. 7, pp. 2668–2693, Mar. 2015.
  •  S. Kotiyal, H. Thapliyal and N. Ranganathan, “Design of Reversible Adder-Subtractor and Its Mapping In Optical Computing Domain”, Springer Transactions on Computational Science XXIV Lecture Notes in Computer Science, Vol. 8911, Jan 2015.
  •  S. Kotiyal, H. Thapliyal and N. Ranganathan, “Efficient reversible NOR gates and their mapping in optical computing domain”, Microelectronics Journal, Vol. 45, No.6, pp. 825-834, June 2014.
  •  C. Labrado, H. Thapliyal, and R. F. Demara, “Design of Testable Adder Circuits for Spintronics Based Nanomagnetic Computing,” in 2015 IEEE International Symposium on Nanoelectronic and Information Systems, 2015, pp. 107–111.
  •  H. Thapliyal, “Circuit design of garbageless reversible multiplier for quantum computing”, Quantum Programming and Circuits Workshop, Waterloo, June 2015
  •  H. Thapliyal and C. Labrado, “Design of Testable Adder Circuits for Spintronics Based Nanomagnetic Computing”,  24th Annual Single Event Effects (SEE) Symposium/ Military and Aerospace Programmable Logic Devices (MAPLD) Workshop, San Diego, May 2015
  • M. H. A. Khan and H. Thapliyal, “Reversible logic based mapping of quaternary sequential circuits using QGFSOP expression,’ Proceedings IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Montpellier, France, July 2015.
  •  H.V. Jayashree, H. Thapliyal and V. Agrawal, “Design of Dedicated Reversible Quantum Circuitry for Square Computation”,  Proceedings of the 27th International Conference on VLSI Design (VLSI Design), Mumbai, India, Jan 2014, pp. 551-556.
  • S. Kotiyal H. Thapliyal and N. Ranganathan, “Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits”, Proceedings of the 27th International Conference on VLSI Design (VLSI Design), Mumbai, India, Jan 2014, pp. 545-550.

YEAR 2013-:

  •  H. Thapliyal and N. Ranganathan, “Design of Efficient Reversible Logic Based Binary and BCD Adder Circuits”, ACM Journal of Emerging Technologies in Computing Systems,Vol.9, No.3,pp. 17:1–17:31, Sep 2013.
  •  H. Thapliyal,  N. Ranganathan and S.Kotiyal, “Design of Testable Reversible Sequential Circuits “, IEEE Transactions on VLSI, vol. 21, no.7,  pp.1201-1209, July 2013
  • H.Thapliyal, H. V. Jayashree, A. N. Nagamani, H.R. Arabnia, “Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead Adder”, Springer Transactions on Computational Science XVII Lecture Notes in Computer Science Volume 7420, 2013, pp 73-97
  • H. Thapliyal and N. Ranganathan, “Design of Reversible Sequential Circuits Optimizing Quantum Cost, Delay and Garbage Outputs”, ACM Journal of Emerging Technologies in Computing Systems, Vol. 6, No. 4, Article 14, Dec 2010
  • H. Thapliyal and N. Ranganathan, “Reversible Logic Based Concurrently Testable Latches for Molecular QCA”, IEEE Transactions on Nanotechnology, vol. 9, No. 1, pp. 62-69, Jan 2010.
  • H. Thapliyal, H.R. Arabnia and M.B. Srinivas, “Efficient Reversible Logic Design of BCD Subtractors”, Springer Transactions on Computational Sciences Journal, Vol. 3, LNCS 5300, pp. 99-121, 2009.
  • H.Thapliyal, A. Bhatt and N. Ranganathan, “A New CRL Gate As a Super Class of Fredkin Gate for Design of Reversible Barrel Shifter”,   Proceedings of the 56th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Columbus, Aug 2013, pp. 1067-1070.
  • H.Thapliyal and N. Ranganathan, “Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies”,   Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Amherst, Aug 2012, pp. 5-6.  (Best  Paper Award)
  •  S.Kotiyal, H.Thapliyal and N. Ranganathan,  “Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates “,   Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Amherst, Aug 2012, March 2012, pp. 207-212.
  • S.Kotiyal, H.Thapliyal and N. Ranganathan, “Mach-Zehnder Interferometer Based Design of All Optical Reversible Binary Adder”,   Proceedings of the Design Automation and Test in Europe (DATE), Dresden, Germany, March 2012, pp. 721-726.
  • H. Thapliyal and N. Ranganathan, “A new design of the reversible subtractor circuit”, Proceedings of the 11th IEEE International Conference on Nanotechnology (IEEE NANO), Portland, Oregon, August 2011, pp.1430-1435.
  • S. Kotiyal, H. Thapliyal, and N. Ranganathan, “Design of a reversible bidirectional barrel shifter”, Proceedings of the   11th IEEE International Conference on Nanotechnology (IEEE NANO), Portland, Oregon, August 2011, 463-468.
  • M. Nachtigal, H. Thapliyal, and N. Ranganathan, “Design of a reversible floating-point adder architecture”, Proceedings of the  11th IEEE International Conference on Nanotechnology (IEEE NANO), Portland, Oregon, August 2011, pp. 451-456.
  • H. Thapliyal and N. Ranganathan, “ A New Reversible Design of BCD Adder”, Proceedings  of  Design Automation and Test in Europe (DATE), Grenoble, France, March 2011, pp.1180-1183.
  • H. Thapliyal, N. Ranganathan and R. Ferreira, “Design of a Comparator Tree Based on Reversible Logic”, Proceedings of the 10th IEEE International Conference on Nanotechnology (IEEE NANO), Seoul, Korea, Aug 2010, pp. 1113-1116.
  • H. Thapliyal and N.Ranganathan, “Reversible Logic Based Concurrent Error Detection Methodology For Emerging Nanocircuits”, Proceedings  of the 10th  IEEE International Conference on Nanotechnology  (IEEE NANO),Seoul, Korea, Aug 2010, pp.217-222.
  • M. Nachtigal, H. Thapliyal and N. Ranganathan,  “Design of a Reversible Single Precision Floating Point Multiplier Based on Operand Decomposition”,   Proceedings of the 10th  IEEE International Conference on Nanotechnology (IEEE NANO), Seoul, Korea, Aug 2010,pp.233-237.
  • S.  Kotiyal, H. Thapliyal and  N. Ranganathan,  “Design of A Ternary Barrel Shifter Using Multiple-Valued Reversible Logic”, Proceedings  of the 10th  IEEE International Conference on Nanotechnology (IEEE NANO), Seoul, Korea, Aug 2010,pp.1104-1108.
  • H. Thapliyal and N. Ranganathan, “Design of Reversible Latches Optimized for Quantum Cost,Delay and Garbage Outputs”, Proceedings of  the 23rd International Conference on  VLSI Design (VLSI Design) , Bangalore, India,  Jan 2010,pp.235-240.
  •  H. Thapliyal and N. Ranganathan, ”Bit Conserving Logic as a Potential Integration Platform for Hybrid Molecular & Nanoscale CMOS-Based Architectures”, Proceedings  of the 2009 Nanoelectronic Devices for Defense & Security (NANO-DDS) Conference, Fort Lauderdale, Sept 2009.
  • H. Thapliyal and N. Ranganathan, “Concurrently Testable FPGA Design for Molecular QCA Using Conservative Reversible Logic Gate”, Proceedings of the International Symposium on Circuits and Systems (ISCAS), Taipei, May 2009, pp. 1815 – 1818.
  •  H. Thapliyal and N. Ranganathan, “Design of Efficient Reversible Binary Subtractors Based on A New Reversible Gate “,   Proceedings  of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, May 2009, pp.239-234.
  • H. Thapliyal and N. Ranganathan, ” Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits”,  Proceedings of the 22nd International Conference on  VLSI Design (VLSI Design), Delhi, India, Jan 2009, pp.511-516.
  • H. Thapliyal and N. Ranganathan, “Testable Reversible Latches for Molecular QCA”, Proceedings of the 8th International Conference on Nanotechnology (IEEE NANO), Arlington, TX, Aug 2008. pp. 699-702 (Invited Paper).
  • H. Thapliyal and A. P. Vinod, “Design of Reversible Sequential Elements with Feasibility of Transistor Implementation”, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), New Orleans, USA, May 2007, pp. 625-628.
  • H. Thapliyal and A. P. Vinod, “Designing Efficient Online Testable Reversible Adders with New Reversible Gate”, Proceedings  of the IEEE International Symposium on Circuits and Systems (ISCAS), New Orleans, USA, May 2007, pp.1085-1088
  • H. Thapliyal, H.R. Arabnia and A.P.Vinod, “Combined Integer and Floating Point Multiplication Architecture (CIFM) for FPGAs and its Reversible Logic Implementation”, Proceedings of the 49th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Puerto Rico,  Aug 2006,
    pp. 438-442 (Best Student Paper Award Finalist).
  •  H. Thapliyal and M.B Srinivas, “Reversible Logic Implementation of BCD Subtractor for IEEE 754r Format”, Proceedings of the 15th ACM SIGDA International Workshop on Logic & Synthesis (IWLS ), Colorado, USA, June 7-9, 2006.
  •  H. Thapliyal and M. Zwolinski, “Reversible Logic to Cryptographic Hardware: A New Paradigm”, Proceedings of the 49th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Puerto Rico, Aug 2006, pp. 342-346 (Best Student Paper Award Finalist). 
  • H. Thapliyal and M.B. Srinivas, “The New BCD Subtractor and Its Reversible Logic Implementation”, Springer-Verlag Lecture Notes in Computer Science, Proceedings of the 11th Asia-Pacific Computer Systems Architecture Conference – ACSAC, Vol. 4186/2006, pp. 469-475, Sep 2006
  •  H. Thapliyal and M.B. Srinivas et al., “Modified Montgomery Modular Multiplication Using 4:2 Compressor And CSA Adder”, Proceedings of the  3rd IEEE International Workshop on Electronic Design, Test and Applications (DELTA) , Kuala Lumpur, Malaysia, Jan 2006, pp. 414-417.
  • H. Thapliyal, S. Kotiyal and M.B. Srinivas, “Novel BCD Adders and their Reversible Logic Implementation for IEEE 754r Format”, Proceedings of the 19th  IEEE/ACM International Conference on VLSI Design (VLSI Design), Hyderabad, India, Jan 4-7, 2006, pp. 387-392.
  • H. Thapliyal and M.B. Srinivas, “Novel Reversible “TSG” Gate and Its Application for Designing Reversible Carry Look Ahead Adder and Other Adder Architectures”, Springer-Verlag Lecture Notes in Computer Science , Proceedings of the 10th Asia-Pacific Computer Systems Architecture Conference – ACSAC,vol. 3740/2005, pp. 775-786, October 2005.
  •  H. Thapliyal and M.B. Srinivas ,”An Efficient Method of Elliptic Curve Encryption Using Ancient Indian Vedic Mathematics”, Proceedings of the 48th IEEE MIDWEST Symposium on Circuits and Systems (MWSCAS 2005), Cincinnati, Ohio, USA, August 7-10, 2005, pp. 826-829.
  •  H.  Thapliyal, M. B. Srinivas and M. Zwolinski, “A Beginning in the Reversible Logic Synthesis of Sequential Circuits,” Proceedings of NASA Military and Aerospace Programmable Logic Devices (MAPLD) International Conference, Sep 2005.