## Vedic Maths

**SELECTED PUBLICATIONS ON VEDIC MATHEMATICS**

- Himanshu Thapliyal and M.B Srinivas,
*“**High Speed Efficient N X N Bit Parallel Hierarchical Overlay Multiplier Architecture Based On Ancient Indian Vedic Mathematics”*Enformatika (Transactions on Engineering, Computing and Technology),Volume 2,Dec 2004, pp.225-228.**,** - Himanshu Thapliyal and M.B Srinivas ,
*”An Efficient Method of Elliptic Curve Encryption Using Ancient Indian Vedic Mathematics”*, Proceedings of the 48th IEEE MIDWEST Symposium on Circuits and Systems (MWSCAS 2005), Cincinnati, Ohio, USA, August 7-10, 2005, pp. 826-829. IEEE Press. - Himanshu Thapliyal and M.B Srinivas ,
*”Design and Analysis of A Novel Parallel Square and Cube Architecture Based On Ancient Indian Vedic Mathematics*“, Proceedings of the 48th IEEE MIDWEST Symposium on Circuits and Systems (MWSCAS 2005), Cincinnati, Ohio, USA, August 7-10, 2005, pp.1462-1465. IEEE Press. - Himanshu Thapliyal and M.B Srinivas,
*“VLSI Implementation of RSA Encryption System using Ancient Indian Vedic Mathematics ”*, Proceedings of SPIE — Volume 5837 VLSI Circuits and Systems II, Jose F. Lopez, Francisco V. Fernandez, Jose Maria Lopez-Villegas, Jose M. de la Rosa, Editors, June 2005, pp. 888-892 - Himanshu Thapliyal and Hamid R. Arabnia,
*“High Speed Efficient N Bit by N Bit Division Algorithm And Architecture Based On Ancient Indian Vedic Mathematics**“,*Proceedings of VLSI04, Las Vegas, U.S.A, June 2004, pp. 413-419(CSREA Press). - Himanshu Thapliyal and Hamid R. Arabnia,
*“**A Novel Parallel Multiply and Accumulate (V-MAC) Architecture Based on Ancient Indian Vedic Mathematics”*, Proceedings of VLSI04, Las Vegas , U.S.A, June 2004, pp. 440-446(CSREA Press). - Himanshu Thapliyal and Hamid R. Arabnia,
*“**A Time-Area-Power Efficient Multiplier and Square Architecture Based on Ancient Indian Vedic Mathematics”*, Proceedings of VLSI04, Las Vegas , U.S.A, June 2004, pp. 434-439(CSREA Press). - Himanshu Thapliyal, “
*Novel Design of NXN Bit Decomposed Multiplier Based on Ancient Vedic Mathematics”*, Proceedings of the 3rd UK ACM SIGDA Workshop on Electronic Design Automation, Southampton, U.K., Sep 2003.

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**CREATOR RESEARCH GROUP ON VEDIC MATHEMATICS IN FACEBOOK**

Himanshu Thapliyal has formed a Vedic mathematics research group in Facebook.

You are invited to join the group. **CLICK HERE TO JOIN THE GROUP **or Visit http://www.facebook.com/group.php?gid=125003206773&ref=nf

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**RECENT TALKS ON VEDIC MATHEMATICS**

- Math By Mind! High Speed Mathematics, Liberty High school, Tampa, Florida, Nov 2010
- Vedic Mathematics for Faster Mental Calculations and High Speed Computing, Foundation of Engineering Course, Dec 2009
- Introduction to Vedic Mathematics, Engineering Expo, Feb 2010 ( Engineering Expo is attended by Elementary and high school students and their parents)
- Workshop on Vedic Mathematics, Fresno , California – May 2009 (Invited by Dr. Ram Nunna, Associate Dean, Lyles College of Engineering, California State University, Fresno)
- Vedic Mathematics for Faster Mental Calculations and High Speed VLSI Arithmetic, IEEE Computer Society Student Chapter, University of South Florida, Tampa, FL, Nov 2008.

**ABSTRACT AND SLIDES OF TALK: VEDIC MATHEMATICS FOR FASTER MENTAL CALCULATIONS AND HIGH SPEED VLSI ARITHMETIC**

This presentation will introduce ancient Indian Vedic Mathematics for faster mental calculation and high-speed VLSI arithmetic. Vedic math algorithms such as multiplication, division, square, cube etc. will be illustrated with examples. Unconventional techniques to perform faster mental calculations will be demonstrated. The influence and application of Vedic mathematics in design of high speed VLSI arithmetic circuits will also be discussed. **CLICK HERE TO SEE THE PRESENTATION**

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**To refer to (cite) this presentation, the following style should be used: **

**Himanshu**** Thapliyal, “Vedic Mathematics for Faster Mental Calculations and High Speed VLSI Arithmetic”, Invited talk at IEEE Computer Society Student Chapter, University of South Florida, Tampa, FL, Nov 14 2008.**